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NOIL2SM1300A
Analog Front End
Programmable Gain Amplifiers
The PGAs amplify the signal before sending it to the
ADCs.
Analog to Digital Converter
The sensor has 24 10-bit pipelined ADCs on board. The
ADCs nominally operate at 31.5 Msamples/s.
The amplification inside the PGA is controlled by one SPI
setting: afemode [5:3].
Six gain steps can be selected by the afemode<5:3>
register.
Table 7 lists the six gain settings. The unity gain selection
of the PGA is done by the default afemode<5:3> setting.
Table 7. GAIN SETTINGS
Table 8. ADC PARAMETERS
Parameter
Data rate
Quantization
DNL
INL
Specification
31.5 Msamples/s
10 bit
Typ. < 1 DN
Typ. < 1 DN
afemode<5:3>
000
001
010
011
100
101
Gain
1
1.5
2
2.25
3
4
Data Block
The data block is positioned in between the analog front
end (output stage + ADCs) and the LVDS interface. It muxes
the outputs of two ADCs to one LVDS block and performs
some minor data handling:
? CRC calculation and insertion
? Training and test pattern generation
It also contains a huge part of the functionality for black
level calibration and FPN correction.
A number of data blocks are placed in parallel to serve all
data output channels. One additional channel generates the
synchronization protocol. A high level overview is
illustrated in the following figure.
Figure 7. Data Block
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